# DO NOT UNCOMMENT the following line. sysclk constrained by MIG
# create_clock -period 10.000 -waveform {0.000 5.000} [get_ports SYSCLK]
# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets SYSCLK]

# 108 MHz is the pixel clock for 1280x1024
#create_clock -period 9.259 -waveform {0.000 5.000} [get_ports hdmi_rx_clk_p]


set_property PACKAGE_PIN T4 [get_ports SDATA_I]
set_property IOSTANDARD LVCMOS33 [get_ports SDATA_I]
set_property PACKAGE_PIN T5 [get_ports BCLK_O]
set_property IOSTANDARD LVCMOS33 [get_ports BCLK_O]
set_property PACKAGE_PIN W6 [get_ports SDATA_O]
set_property IOSTANDARD LVCMOS33 [get_ports SDATA_O]
set_property PACKAGE_PIN U5 [get_ports LRCLK_O]
set_property IOSTANDARD LVCMOS33 [get_ports LRCLK_O]
set_property PACKAGE_PIN U6 [get_ports MCLK_O]
set_property IOSTANDARD LVCMOS33 [get_ports MCLK_O]
set_property PACKAGE_PIN B22 [get_ports {btn[4]}]
set_property IOSTANDARD LVCMOS12 [get_ports {btn[4]}]
set_property PACKAGE_PIN D22 [get_ports {btn[3]}]
set_property IOSTANDARD LVCMOS12 [get_ports {btn[3]}]
set_property PACKAGE_PIN C22 [get_ports {btn[2]}]
set_property IOSTANDARD LVCMOS12 [get_ports {btn[2]}]
set_property PACKAGE_PIN D14 [get_ports {btn[1]}]
set_property IOSTANDARD LVCMOS12 [get_ports {btn[1]}]
set_property PACKAGE_PIN F15 [get_ports {btn[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports {btn[0]}]

#set_property PACKAGE_PIN G4 [get_ports CPU_RESETN]
#set_property IOSTANDARD LVCMOS15 [get_ports CPU_RESETN]
##set_property -dict { PACKAGE_PIN M2   } [get_ports { DDR3_ADDR[0] }]; #IO_L16N_T2_35 Sch=ddr3_addr[0]
#set_property -dict { PACKAGE_PIN M5   } [get_ports { DDR3_ADDR[1] }]; #IO_L23N_T3_35 Sch=ddr3_addr[1]
#set_property -dict { PACKAGE_PIN L5   } [get_ports { DDR3_ADDR[10] }]; #IO_L18P_T2_35 Sch=ddr3_addr[10]
#set_property -dict { PACKAGE_PIN N5   } [get_ports { DDR3_ADDR[11] }]; #IO_L24N_T3_35 Sch=ddr3_addr[11]
#set_property -dict { PACKAGE_PIN N4   } [get_ports { DDR3_ADDR[12] }]; #IO_L19P_T3_35 Sch=ddr3_addr[12]
#set_property -dict { PACKAGE_PIN P2   } [get_ports { DDR3_ADDR[13] }]; #IO_L22P_T3_35 Sch=ddr3_addr[13]
#set_property -dict { PACKAGE_PIN P6   } [get_ports { DDR3_ADDR[14] }]; #IO_L24P_T3_35 Sch=ddr3_addr[14]
#set_property -dict { PACKAGE_PIN M3   } [get_ports { DDR3_ADDR[2] }]; #IO_L16P_T2_35 Sch=ddr3_addr[2]
#set_property -dict { PACKAGE_PIN M1   } [get_ports { DDR3_ADDR[3] }]; #IO_L15P_T2_DQS_35 Sch=ddr3_addr[3]
#set_property -dict { PACKAGE_PIN L6   } [get_ports { DDR3_ADDR[4] }]; #IO_25_35 Sch=ddr3_addr[4]
#set_property -dict { PACKAGE_PIN P1   } [get_ports { DDR3_ADDR[5] }]; #IO_L20N_T3_35 Sch=ddr3_addr[5]
#set_property -dict { PACKAGE_PIN N3   } [get_ports { DDR3_ADDR[6] }]; #IO_L19N_T3_VREF_35 Sch=ddr3_addr[6]
#set_property -dict { PACKAGE_PIN N2   } [get_ports { DDR3_ADDR[7] }]; #IO_L22N_T3_35 Sch=ddr3_addr[7]
#set_property -dict { PACKAGE_PIN M6   } [get_ports { DDR3_ADDR[8] }]; #IO_L23P_T3_35 Sch=ddr3_addr[8]
#set_property -dict { PACKAGE_PIN R1   } [get_ports { DDR3_ADDR[9] }]; #IO_L20P_T3_35 Sch=ddr3_addr[9]
#set_property -dict { PACKAGE_PIN L3   } [get_ports { DDR3_BA[0] }]; #IO_L14P_T2_SRCC_35 Sch=ddr3_ba[0]
#set_property -dict { PACKAGE_PIN K6   } [get_ports { DDR3_BA[1] }]; #IO_L17P_T2_35 Sch=ddr3_ba[1]
#set_property -dict { PACKAGE_PIN L4   } [get_ports { DDR3_BA[2] }]; #IO_L18N_T2_35 Sch=ddr3_ba[2]
#set_property -dict { PACKAGE_PIN K3   } [get_ports { DDR3_CAS }]; #IO_L14N_T2_SRCC_35 Sch=ddr3_cas
#set_property -dict { PACKAGE_PIN J6   } [get_ports { DDR3_CKE[0] }]; #IO_L17N_T2_35 Sch=ddr3_cke[0]
#set_property -dict { PACKAGE_PIN P4    IOSTANDARD LVDS     } [get_ports { DDR3_CLK_N[0] }]; #IO_L21N_T3_DQS_35 Sch=ddr3_clk_n[0]
#set_property -dict { PACKAGE_PIN P5    IOSTANDARD LVDS     } [get_ports { DDR3_CLK_P[0] }]; #IO_L21P_T3_DQS_35 Sch=ddr3_clk_p[0]
#set_property -dict { PACKAGE_PIN G3   } [get_ports { DDR3_DM[0] }]; #IO_L11N_T1_SRCC_35 Sch=ddr3_dm[0]
#set_property -dict { PACKAGE_PIN F1   } [get_ports { DDR3_DM[1] }]; #IO_L5N_T0_AD13N_35 Sch=ddr3_dm[1]
#set_property -dict { PACKAGE_PIN G2   } [get_ports { DDR3_DQ[0] }]; #IO_L8N_T1_AD14N_35 Sch=ddr3_dq[0]
#set_property -dict { PACKAGE_PIN H4   } [get_ports { DDR3_DQ[1] }]; #IO_L12P_T1_MRCC_35 Sch=ddr3_dq[1]
#set_property -dict { PACKAGE_PIN F3   } [get_ports { DDR3_DQ[10] }]; #IO_L6P_T0_35 Sch=ddr3_dq[10]
#set_property -dict { PACKAGE_PIN D2   } [get_ports { DDR3_DQ[11] }]; #IO_L4N_T0_35 Sch=ddr3_dq[11]
#set_property -dict { PACKAGE_PIN C2   } [get_ports { DDR3_DQ[12] }]; #IO_L2P_T0_AD12P_35 Sch=ddr3_dq[12]
#set_property -dict { PACKAGE_PIN A1   } [get_ports { DDR3_DQ[13] }]; #IO_L1N_T0_AD4N_35 Sch=ddr3_dq[13]
#set_property -dict { PACKAGE_PIN E2   } [get_ports { DDR3_DQ[14] }]; #IO_L4P_T0_35 Sch=ddr3_dq[14]
#set_property -dict { PACKAGE_PIN B1   } [get_ports { DDR3_DQ[15] }]; #IO_L1P_T0_AD4P_35 Sch=ddr3_dq[15]
#set_property -dict { PACKAGE_PIN H5   } [get_ports { DDR3_DQ[2] }]; #IO_L10N_T1_AD15N_35 Sch=ddr3_dq[2]
#set_property -dict { PACKAGE_PIN J1   } [get_ports { DDR3_DQ[3] }]; #IO_L7N_T1_AD6N_35 Sch=ddr3_dq[3]
#set_property -dict { PACKAGE_PIN K1   } [get_ports { DDR3_DQ[4] }]; #IO_L7P_T1_AD6P_35 Sch=ddr3_dq[4]
#set_property -dict { PACKAGE_PIN H3   } [get_ports { DDR3_DQ[5] }]; #IO_L11P_T1_SRCC_35 Sch=ddr3_dq[5]
#set_property -dict { PACKAGE_PIN H2   } [get_ports { DDR3_DQ[6] }]; #IO_L8P_T1_AD14P_35 Sch=ddr3_dq[6]
#set_property -dict { PACKAGE_PIN J5   } [get_ports { DDR3_DQ[7] }]; #IO_L10P_T1_AD15P_35 Sch=ddr3_dq[7]
#set_property -dict { PACKAGE_PIN E3   } [get_ports { DDR3_DQ[8] }]; #IO_L6N_T0_VREF_35 Sch=ddr3_dq[8]
#set_property -dict { PACKAGE_PIN B2   } [get_ports { DDR3_DQ[9] }]; #IO_L2N_T0_AD12N_35 Sch=ddr3_dq[9]
#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVDS     } [get_ports { DDR3_DQS_N[0] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ddr3_dqs_n[0]
#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVDS     } [get_ports { DDR3_DQS_P[0] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ddr3_dqs_p[0]
#set_property -dict { PACKAGE_PIN D1    IOSTANDARD LVDS     } [get_ports { DDR3_DQS_N[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ddr3_dqs_n[1]
#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVDS     } [get_ports { DDR3_DQS_P[1] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ddr3_dqs_p[1]
#set_property -dict { PACKAGE_PIN K4   } [get_ports { DDR3_ODT }]; #IO_L13P_T2_MRCC_35 Sch=ddr3_odt
#set_property -dict { PACKAGE_PIN J4   } [get_ports { DDR3_RAS }]; #IO_L13N_T2_MRCC_35 Sch=ddr3_ras
#set_property -dict { PACKAGE_PIN G1   } [get_ports { DDR3_RESET }]; #IO_L5P_T0_AD13P_35 Sch=ddr3_reset
#set_property -dict { PACKAGE_PIN L1   } [get_ports { DDR3_WE }]; #IO_L15N_T2_DQS_35 Sch=ddr3_we
#set_property -dict { PACKAGE_PIN AB10  IOSTANDARD LVDS     } [get_ports { DP_TX_AUX_N }]; #IO_L8N_T1_13 Sch=dp_tx_aux_n
#set_property -dict { PACKAGE_PIN AA11  IOSTANDARD LVDS     } [get_ports { DP_TX_AUX_N }]; #IO_L9N_T1_DQS_13 Sch=dp_tx_aux_n
#set_property -dict { PACKAGE_PIN AA9   IOSTANDARD LVDS     } [get_ports { DP_TX_AUX_P }]; #IO_L8P_T1_13 Sch=dp_tx_aux_p
#set_property -dict { PACKAGE_PIN AA10  IOSTANDARD LVDS     } [get_ports { DP_TX_AUX_P }]; #IO_L9P_T1_DQS_13 Sch=dp_tx_aux_p
#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { DP_TX_HPD }]; #IO_25_14 Sch=dp_tx_hpd

#set_property PACKAGE_PIN Y14 [get_ports ETH_INT_B]
#set_property IOSTANDARD LVCMOS25 [get_ports ETH_INT_B]
#set_property PACKAGE_PIN AA16 [get_ports ETHM_mdc]
#set_property IOSTANDARD LVCMOS25 [get_ports ETHM_mdc]
#set_property PACKAGE_PIN Y16 [get_ports ETHM_io]
#set_property IOSTANDARD LVCMOS25 [get_ports ETHM_io]
##set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS25 } [get_ports { ETH_PME_B }]; #IO_L6P_T0_13 Sch=eth_pme_b
#set_property PACKAGE_PIN U7 [get_ports ETH_RST_B]
#set_property IOSTANDARD LVCMOS33 [get_ports ETH_RST_B]
#set_property PACKAGE_PIN V13 [get_ports ETH_rxc]
#set_property IOSTANDARD LVCMOS25 [get_ports ETH_rxc]
#set_property PACKAGE_PIN W10 [get_ports ETH_rx_ctl]
#set_property IOSTANDARD LVCMOS25 [get_ports ETH_rx_ctl]
#set_property PACKAGE_PIN AB16 [get_ports {ETH_rd[0]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {ETH_rd[0]}]
#set_property PACKAGE_PIN AA15 [get_ports {ETH_rd[1]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {ETH_rd[1]}]
#set_property PACKAGE_PIN AB15 [get_ports {ETH_rd[2]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {ETH_rd[2]}]
#set_property PACKAGE_PIN AB11 [get_ports {ETH_rd[3]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {ETH_rd[3]}]
#set_property PACKAGE_PIN AA14 [get_ports ETH_txc]
#set_property IOSTANDARD LVCMOS25 [get_ports ETH_txc]
#set_property PACKAGE_PIN V10 [get_ports ETH_tx_ctl]
#set_property IOSTANDARD LVCMOS25 [get_ports ETH_tx_ctl]
#set_property PACKAGE_PIN Y12 [get_ports {ETH_td[0]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {ETH_td[0]}]
#set_property PACKAGE_PIN W12 [get_ports {ETH_td[1]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {ETH_td[1]}]
#set_property PACKAGE_PIN W11 [get_ports {ETH_td[2]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {ETH_td[2]}]
#set_property PACKAGE_PIN Y11 [get_ports {ETH_td[3]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {ETH_td[3]}]

## fmc clks
#set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVDS_25  } [get_ports { EXT_SIG_0_I_N }]; #IO_L12N_T1_MRCC_15 Sch=fmc_clk0_m2c_n
#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVDS_25  } [get_ports { EXT_SIG_0_I_P }]; #IO_L12P_T1_MRCC_15 Sch=fmc_clk0_m2c_p
#set_property -dict { PACKAGE_PIN C19   IOSTANDARD LVDS_25  } [get_ports { EXT_SIG_1_I_N }]; #IO_L13N_T2_MRCC_16 Sch=fmc_clk1_m2c_n
#set_property -dict { PACKAGE_PIN C18   IOSTANDARD LVDS_25  } [get_ports { EXT_SIG_1_I_P }]; #IO_L13P_T2_MRCC_16 Sch=fmc_clk1_m2c_p

## la_n even
#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[0] }]; #IO_L13N_T2_MRCC_15 Sch=fmc_la00_cc_n
#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[1] }]; #IO_L16N_T2_A27_15 Sch=fmc_la_n[02]
#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[2] }]; #IO_L18N_T2_A23_15 Sch=fmc_la_n[04]
#set_property -dict { PACKAGE_PIN M22   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[3] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_la_n[06]
#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[4] }]; #IO_L24N_T3_RS0_15 Sch=fmc_la_n[08]
#set_property -dict { PACKAGE_PIN K22   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[5] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=fmc_la_n[10]
#set_property -dict { PACKAGE_PIN L20   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[6] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_la_n[12]
#set_property -dict { PACKAGE_PIN H22   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[7] }]; #IO_L7N_T1_AD2N_15 Sch=fmc_la_n[14]
#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[8] }]; #IO_L4N_T0_15 Sch=fmc_la_n[16]
#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[9] }]; #IO_L12N_T1_MRCC_16 Sch=fmc_la18_cc_n
#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[10] }]; #IO_L18N_T2_16 Sch=fmc_la_n[20]
#set_property -dict { PACKAGE_PIN D21   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[11] }]; #IO_L23N_T3_16 Sch=fmc_la_n[22]
#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[12] }]; #IO_L7N_T1_16 Sch=fmc_la_n[24]
#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[13] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[26]
#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[14] }]; #IO_L8N_T1_16 Sch=fmc_la_n[28]
#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[15] }]; #IO_L10N_T1_16 Sch=fmc_la_n[30]
#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_n_tri_io[16] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[32]
#set_property SLEW SLOW [get_ports { fmc_la_00_32_n_tri_io[*] }];
#set_property DRIVE 4 [get_ports { fmc_la_00_32_n_tri_io[*] }];
#set_property PULLUP TRUE [get_ports { fmc_la_00_32_n_tri_io[*] }];
### la_n odd
#set_property -dict { PACKAGE_PIN J21   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[0] }]; #IO_L11N_T1_SRCC_15 Sch=fmc_la01_cc_n
#set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[1] }]; #IO_L17N_T2_A25_15 Sch=fmc_la_n[03]
#set_property -dict { PACKAGE_PIN L21   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[2] }]; #IO_L10N_T1_AD11N_15 Sch=fmc_la_n[05]
#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[3] }]; #IO_L20N_T3_A19_15 Sch=fmc_la_n[07]
#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[4] }]; #IO_L8N_T1_AD10N_15 Sch=fmc_la_n[09]
#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[5] }]; #IO_L22N_T3_A16_15 Sch=fmc_la_n[11]
#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[6] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_la_n[13]
#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[7] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_la_n[15]
#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[8] }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la17_cc_n
#set_property -dict { PACKAGE_PIN A19   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[9] }]; #IO_L17N_T2_16 Sch=fmc_la_n[19]
#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[10] }]; #IO_L14N_T2_SRCC_16 Sch=fmc_la_n[21]
#set_property -dict { PACKAGE_PIN A21   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[11] }]; #IO_L21N_T3_DQS_16 Sch=fmc_la_n[23]
#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[12] }]; #IO_L2N_T0_16 Sch=fmc_la_n[25]
#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[13] }]; #IO_L16N_T2_16 Sch=fmc_la_n[27]
#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[14] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[29]
#set_property -dict { PACKAGE_PIN E14   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[15] }]; #IO_L4N_T0_16 Sch=fmc_la_n[31]
#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_n_tri_io[16] }]; #IO_L1N_T0_16 Sch=fmc_la_n[33]
#set_property SLEW SLOW [get_ports { fmc_la_01_33_n_tri_io[*] }];
#set_property DRIVE 4 [get_ports { fmc_la_01_33_n_tri_io[*] }];
#set_property PULLUP TRUE [get_ports { fmc_la_01_33_n_tri_io[*] }];
### la_p even
#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[0] }]; #IO_L13P_T2_MRCC_15 Sch=fmc_la00_cc_p
#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[1] }]; #IO_L16P_T2_A28_15 Sch=fmc_la_p[02]
#set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[2] }]; #IO_L18P_T2_A24_15 Sch=fmc_la_p[04]
#set_property -dict { PACKAGE_PIN N22   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[3] }]; #IO_L15P_T2_DQS_15 Sch=fmc_la_p[06]
#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[4] }]; #IO_L24P_T3_RS1_15 Sch=fmc_la_p[08]
#set_property -dict { PACKAGE_PIN K21   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[5] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=fmc_la_p[10]
#set_property -dict { PACKAGE_PIN L19   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[6] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_la_p[12]
#set_property -dict { PACKAGE_PIN J22   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[7] }]; #IO_L7P_T1_AD2P_15 Sch=fmc_la_p[14]
#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[8] }]; #IO_L4P_T0_15 Sch=fmc_la_p[16]
#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[9] }]; #IO_L12P_T1_MRCC_16 Sch=fmc_la18_cc_p
#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[10] }]; #IO_L18P_T2_16 Sch=fmc_la_p[20]
#set_property -dict { PACKAGE_PIN E21   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[11] }]; #IO_L23P_T3_16 Sch=fmc_la_p[22]
#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[12] }]; #IO_L7P_T1_16 Sch=fmc_la_p[24]
#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[13] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[26]
#set_property -dict { PACKAGE_PIN C13   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[14] }]; #IO_L8P_T1_16 Sch=fmc_la_p[28]
#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[15] }]; #IO_L10P_T1_16 Sch=fmc_la_p[30]
#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_00_32_p_tri_io[16] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[32]
#set_property SLEW SLOW [get_ports { fmc_la_00_32_p_tri_io[*] }];
#set_property DRIVE 4 [get_ports { fmc_la_00_32_p_tri_io[*] }];
#set_property PULLUP TRUE [get_ports { fmc_la_00_32_p_tri_io[*] }];
### la_p odd
#set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[0] }]; #IO_L11P_T1_SRCC_15 Sch=fmc_la01_cc_p
#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[1] }]; #IO_L17P_T2_A26_15 Sch=fmc_la_p[03]
#set_property -dict { PACKAGE_PIN M21   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[2] }]; #IO_L10P_T1_AD11P_15 Sch=fmc_la_p[05]
#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[3] }]; #IO_L20P_T3_A20_15 Sch=fmc_la_p[07]
#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[4] }]; #IO_L8P_T1_AD10P_15 Sch=fmc_la_p[09]
#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[5] }]; #IO_L22P_T3_A17_15 Sch=fmc_la_p[11]
#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[6] }]; #IO_L21P_T3_DQS_15 Sch=fmc_la_p[13]
#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[7] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_la_p[15]
#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[8] }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la17_cc_p
#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[9] }]; #IO_L17P_T2_16 Sch=fmc_la_p[19]
#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[10] }]; #IO_L14P_T2_SRCC_16 Sch=fmc_la_p[21]
#set_property -dict { PACKAGE_PIN B21   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[11] }]; #IO_L21P_T3_DQS_16 Sch=fmc_la_p[23]
#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[12] }]; #IO_L2P_T0_16 Sch=fmc_la_p[25]
#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[13] }]; #IO_L16P_T2_16 Sch=fmc_la_p[27]
#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[14] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[29]
#set_property -dict { PACKAGE_PIN E13   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[15] }]; #IO_L4P_T0_16 Sch=fmc_la_p[31]
#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS25 } [get_ports { fmc_la_01_33_p_tri_io[16] }]; #IO_L1P_T0_16 Sch=fmc_la_p[33]
#set_property SLEW SLOW [get_ports { fmc_la_01_33_p_tri_io[*] }];
#set_property DRIVE 4 [get_ports { fmc_la_01_33_p_tri_io[*] }];
#set_property PULLUP TRUE [get_ports { fmc_la_01_33_p_tri_io[*] }];

#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS25 } [get_ports { FAN_PWM }]; #IO_L14P_T2_SRCC_13 Sch=fan_pwm
#set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVDS     } [get_ports { FMC_CLK0_M2C_N }]; #IO_L12N_T1_MRCC_15 Sch=fmc_clk0_m2c_n
#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVDS     } [get_ports { FMC_CLK0_M2C_P }]; #IO_L12P_T1_MRCC_15 Sch=fmc_clk0_m2c_p
#set_property -dict { PACKAGE_PIN C19   IOSTANDARD LVDS     } [get_ports { FMC_CLK1_M2C_N }]; #IO_L13N_T2_MRCC_16 Sch=fmc_clk1_m2c_n
#set_property -dict { PACKAGE_PIN C18   IOSTANDARD LVDS     } [get_ports { FMC_CLK1_M2C_P }]; #IO_L13P_T2_MRCC_16 Sch=fmc_clk1_m2c_p
#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVDS     } [get_ports { FMC_LA00_CC_N }]; #IO_L13N_T2_MRCC_15 Sch=fmc_la00_cc_n
#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVDS     } [get_ports { FMC_LA00_CC_P }]; #IO_L13P_T2_MRCC_15 Sch=fmc_la00_cc_p
#set_property -dict { PACKAGE_PIN J21   IOSTANDARD LVDS     } [get_ports { FMC_LA01_CC_N }]; #IO_L11N_T1_SRCC_15 Sch=fmc_la01_cc_n
#set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVDS     } [get_ports { FMC_LA01_CC_P }]; #IO_L11P_T1_SRCC_15 Sch=fmc_la01_cc_p
#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[02] }]; #IO_L16N_T2_A27_15 Sch=fmc_la_n[02]
#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[02] }]; #IO_L16P_T2_A28_15 Sch=fmc_la_p[02]
#set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[03] }]; #IO_L17N_T2_A25_15 Sch=fmc_la_n[03]
#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[03] }]; #IO_L17P_T2_A26_15 Sch=fmc_la_p[03]
#set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[04] }]; #IO_L18N_T2_A23_15 Sch=fmc_la_n[04]
#set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[04] }]; #IO_L18P_T2_A24_15 Sch=fmc_la_p[04]
#set_property -dict { PACKAGE_PIN L21   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[05] }]; #IO_L10N_T1_AD11N_15 Sch=fmc_la_n[05]
#set_property -dict { PACKAGE_PIN M21   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[05] }]; #IO_L10P_T1_AD11P_15 Sch=fmc_la_p[05]
#set_property -dict { PACKAGE_PIN M22   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[06] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_la_n[06]
#set_property -dict { PACKAGE_PIN N22   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[06] }]; #IO_L15P_T2_DQS_15 Sch=fmc_la_p[06]
#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[07] }]; #IO_L20N_T3_A19_15 Sch=fmc_la_n[07]
#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[07] }]; #IO_L20P_T3_A20_15 Sch=fmc_la_p[07]
#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[08] }]; #IO_L24N_T3_RS0_15 Sch=fmc_la_n[08]
#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[08] }]; #IO_L24P_T3_RS1_15 Sch=fmc_la_p[08]
#set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[09] }]; #IO_L8N_T1_AD10N_15 Sch=fmc_la_n[09]
#set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[09] }]; #IO_L8P_T1_AD10P_15 Sch=fmc_la_p[09]
#set_property -dict { PACKAGE_PIN K22   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[10] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=fmc_la_n[10]
#set_property -dict { PACKAGE_PIN K21   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[10] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=fmc_la_p[10]
#set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[11] }]; #IO_L22N_T3_A16_15 Sch=fmc_la_n[11]
#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[11] }]; #IO_L22P_T3_A17_15 Sch=fmc_la_p[11]
#set_property -dict { PACKAGE_PIN L20   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[12] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_la_n[12]
#set_property -dict { PACKAGE_PIN L19   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[12] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_la_p[12]
#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[13] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_la_n[13]
#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[13] }]; #IO_L21P_T3_DQS_15 Sch=fmc_la_p[13]
#set_property -dict { PACKAGE_PIN H22   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[14] }]; #IO_L7N_T1_AD2N_15 Sch=fmc_la_n[14]
#set_property -dict { PACKAGE_PIN J22   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[14] }]; #IO_L7P_T1_AD2P_15 Sch=fmc_la_p[14]
#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[15] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_la_n[15]
#set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[15] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_la_p[15]
#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[16] }]; #IO_L4N_T0_15 Sch=fmc_la_n[16]
#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[16] }]; #IO_L4P_T0_15 Sch=fmc_la_p[16]
#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVDS     } [get_ports { FMC_LA17_CC_N }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la17_cc_n
#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVDS     } [get_ports { FMC_LA17_CC_P }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la17_cc_p
#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVDS     } [get_ports { FMC_LA18_CC_N }]; #IO_L12N_T1_MRCC_16 Sch=fmc_la18_cc_n
#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVDS     } [get_ports { FMC_LA18_CC_P }]; #IO_L12P_T1_MRCC_16 Sch=fmc_la18_cc_p
#set_property -dict { PACKAGE_PIN A19   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[19] }]; #IO_L17N_T2_16 Sch=fmc_la_n[19]
#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[19] }]; #IO_L17P_T2_16 Sch=fmc_la_p[19]
#set_property -dict { PACKAGE_PIN F20   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[20] }]; #IO_L18N_T2_16 Sch=fmc_la_n[20]
#set_property -dict { PACKAGE_PIN F19   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[20] }]; #IO_L18P_T2_16 Sch=fmc_la_p[20]
#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[21] }]; #IO_L14N_T2_SRCC_16 Sch=fmc_la_n[21]
#set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[21] }]; #IO_L14P_T2_SRCC_16 Sch=fmc_la_p[21]
#set_property -dict { PACKAGE_PIN D21   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[22] }]; #IO_L23N_T3_16 Sch=fmc_la_n[22]
#set_property -dict { PACKAGE_PIN E21   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[22] }]; #IO_L23P_T3_16 Sch=fmc_la_p[22]
#set_property -dict { PACKAGE_PIN A21   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[23] }]; #IO_L21N_T3_DQS_16 Sch=fmc_la_n[23]
#set_property -dict { PACKAGE_PIN B21   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[23] }]; #IO_L21P_T3_DQS_16 Sch=fmc_la_p[23]
#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[24] }]; #IO_L7N_T1_16 Sch=fmc_la_n[24]
#set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[24] }]; #IO_L7P_T1_16 Sch=fmc_la_p[24]
#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[25] }]; #IO_L2N_T0_16 Sch=fmc_la_n[25]
#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[25] }]; #IO_L2P_T0_16 Sch=fmc_la_p[25]
#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[26] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[26]
#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[26] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[26]
#set_property -dict { PACKAGE_PIN A20   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[27] }]; #IO_L16N_T2_16 Sch=fmc_la_n[27]
#set_property -dict { PACKAGE_PIN B20   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[27] }]; #IO_L16P_T2_16 Sch=fmc_la_p[27]
#set_property -dict { PACKAGE_PIN B13   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[28] }]; #IO_L8N_T1_16 Sch=fmc_la_n[28]
#set_property -dict { PACKAGE_PIN C13   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[28] }]; #IO_L8P_T1_16 Sch=fmc_la_p[28]
#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[29] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[29]
#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[29] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[29]
#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[30] }]; #IO_L10N_T1_16 Sch=fmc_la_n[30]
#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[30] }]; #IO_L10P_T1_16 Sch=fmc_la_p[30]
#set_property -dict { PACKAGE_PIN E14   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[31] }]; #IO_L4N_T0_16 Sch=fmc_la_n[31]
#set_property -dict { PACKAGE_PIN E13   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[31] }]; #IO_L4P_T0_16 Sch=fmc_la_p[31]
#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[32] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[32]
#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[32] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[32]
#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVDS     } [get_ports { FMC_LA_N[33] }]; #IO_L1N_T0_16 Sch=fmc_la_n[33]
#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVDS     } [get_ports { FMC_LA_P[33] }]; #IO_L1P_T0_16 Sch=fmc_la_p[33]
##set_property -dict { PACKAGE_PIN AA5   IOSTANDARD LVCMOS33 } [get_ports { HDMI_RX_CEC }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec
#set_property PACKAGE_PIN AB12 [get_ports hdmi_rx_hpa]
#set_property IOSTANDARD LVCMOS25 [get_ports hdmi_rx_hpa]
#set_property PACKAGE_PIN Y4 [get_ports hdmi_rx_ddc_scl_io]
#set_property IOSTANDARD LVCMOS33 [get_ports hdmi_rx_ddc_scl_io]
#set_property PACKAGE_PIN AB5 [get_ports hdmi_rx_ddc_sda_io]
#set_property IOSTANDARD LVCMOS33 [get_ports hdmi_rx_ddc_sda_io]
#set_property PACKAGE_PIN R3 [get_ports hdmi_rx_txen]
#set_property IOSTANDARD LVCMOS33 [get_ports hdmi_rx_txen]
#set_property IOSTANDARD TMDS_33 [get_ports hdmi_rx_clk_n]
#set_property PACKAGE_PIN V4 [get_ports hdmi_rx_clk_p]
#set_property IOSTANDARD TMDS_33 [get_ports hdmi_rx_clk_p]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_rx_data_n[0]}]
#set_property PACKAGE_PIN Y3 [get_ports {hdmi_rx_data_p[0]}]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_rx_data_p[0]}]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_rx_data_n[1]}]
#set_property PACKAGE_PIN W2 [get_ports {hdmi_rx_data_p[1]}]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_rx_data_p[1]}]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_rx_data_n[2]}]
#set_property PACKAGE_PIN U2 [get_ports {hdmi_rx_data_p[2]}]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_rx_data_p[2]}]
##set_property -dict { PACKAGE_PIN AA4   IOSTANDARD LVCMOS33 } [get_ports { HDMI_TX_CEC }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec
##set_property -dict { PACKAGE_PIN AB13  IOSTANDARD LVCMOS25 } [get_ports { HDMI_TX_HPD }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd
##set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports { HDMI_TX_RSCL }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl
##set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { HDMI_TX_RSDA }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda
#set_property IOSTANDARD TMDS_33 [get_ports hdmi_tx_clk_n]
#set_property PACKAGE_PIN T1 [get_ports hdmi_tx_clk_p]
#set_property IOSTANDARD TMDS_33 [get_ports hdmi_tx_clk_p]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_tx_data_n[0]}]
#set_property PACKAGE_PIN W1 [get_ports {hdmi_tx_data_p[0]}]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_tx_data_p[0]}]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_tx_data_n[1]}]
#set_property PACKAGE_PIN AA1 [get_ports {hdmi_tx_data_p[1]}]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_tx_data_p[1]}]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_tx_data_n[2]}]
#set_property PACKAGE_PIN AB3 [get_ports {hdmi_tx_data_p[2]}]
#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_tx_data_p[2]}]
#set_property PACKAGE_PIN AB22 [get_ports {gpio_rtl_0_tri_io[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[0]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[0]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[0]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[0]}]
#set_property PACKAGE_PIN AB21 [get_ports {gpio_rtl_0_tri_io[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[1]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[1]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[1]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[1]}]
#set_property PACKAGE_PIN AB20 [get_ports {gpio_rtl_0_tri_io[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[2]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[2]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[2]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[2]}]
#set_property PACKAGE_PIN AB18 [get_ports {gpio_rtl_0_tri_io[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[3]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[3]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[3]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[3]}]
#set_property PACKAGE_PIN V9 [get_ports {gpio_rtl_0_tri_io[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[4]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[4]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[4]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[4]}]
#set_property PACKAGE_PIN V8 [get_ports {gpio_rtl_0_tri_io[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[5]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[5]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[5]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[5]}]
#set_property PACKAGE_PIN V7 [get_ports {gpio_rtl_0_tri_io[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[6]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[6]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[6]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[6]}]
#set_property PACKAGE_PIN W7 [get_ports {gpio_rtl_0_tri_io[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[7]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[7]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[7]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[7]}]
#set_property PACKAGE_PIN Y6 [get_ports {gpio_rtl_0_tri_io[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[8]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[8]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[8]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[8]}]
#set_property PACKAGE_PIN AA6 [get_ports {gpio_rtl_0_tri_io[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[9]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[9]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[9]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[9]}]
#set_property PACKAGE_PIN AA8 [get_ports {gpio_rtl_0_tri_io[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[10]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[10]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[10]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[10]}]
#set_property PACKAGE_PIN AB8 [get_ports {gpio_rtl_0_tri_io[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_0_tri_io[11]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[11]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[11]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[11]}]
#set_property PACKAGE_PIN J14 [get_ports {gpio_rtl_0_tri_io[12]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_rtl_0_tri_io[12]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[12]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[12]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[12]}]
#set_property PACKAGE_PIN H13 [get_ports {gpio_rtl_0_tri_io[13]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_rtl_0_tri_io[13]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[13]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[13]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[13]}]
#set_property PACKAGE_PIN G15 [get_ports {gpio_rtl_0_tri_io[14]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_rtl_0_tri_io[14]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[14]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[14]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[14]}]
#set_property PACKAGE_PIN J15 [get_ports {gpio_rtl_0_tri_io[15]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_rtl_0_tri_io[15]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_0_tri_io[15]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_0_tri_io[15]}]
#set_property PULLUP true [get_ports {gpio_rtl_0_tri_io[15]}]

#set_property PACKAGE_PIN Y21 [get_ports {gpio_rtl_tri_io[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[0]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[0]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[0]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[0]}]
#set_property PACKAGE_PIN AA21 [get_ports {gpio_rtl_tri_io[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[1]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[1]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[1]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[1]}]
#set_property PACKAGE_PIN AA20 [get_ports {gpio_rtl_tri_io[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[2]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[2]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[2]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[2]}]
#set_property PACKAGE_PIN AA18 [get_ports {gpio_rtl_tri_io[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[3]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[3]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[3]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[3]}]
#set_property PACKAGE_PIN W9 [get_ports {gpio_rtl_tri_io[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[4]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[4]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[4]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[4]}]
#set_property PACKAGE_PIN Y9 [get_ports {gpio_rtl_tri_io[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[5]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[5]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[5]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[5]}]
#set_property PACKAGE_PIN Y8 [get_ports {gpio_rtl_tri_io[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[6]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[6]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[6]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[6]}]
#set_property PACKAGE_PIN Y7 [get_ports {gpio_rtl_tri_io[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[7]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[7]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[7]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[7]}]
#set_property PACKAGE_PIN R6 [get_ports {gpio_rtl_tri_io[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[8]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[8]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[8]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[8]}]
#set_property PACKAGE_PIN T6 [get_ports {gpio_rtl_tri_io[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[9]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[9]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[9]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[9]}]
#set_property PACKAGE_PIN AB7 [get_ports {gpio_rtl_tri_io[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[10]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[10]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[10]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[10]}]
#set_property PACKAGE_PIN AB6 [get_ports {gpio_rtl_tri_io[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {gpio_rtl_tri_io[11]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[11]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[11]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[11]}]
#set_property PACKAGE_PIN H14 [get_ports {gpio_rtl_tri_io[12]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_rtl_tri_io[12]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[12]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[12]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[12]}]
#set_property PACKAGE_PIN G13 [get_ports {gpio_rtl_tri_io[13]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_rtl_tri_io[13]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[13]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[13]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[13]}]
#set_property PACKAGE_PIN G16 [get_ports {gpio_rtl_tri_io[14]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_rtl_tri_io[14]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[14]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[14]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[14]}]
#set_property PACKAGE_PIN H15 [get_ports {gpio_rtl_tri_io[15]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {gpio_rtl_tri_io[15]}]
#set_property DRIVE 4 [get_ports {gpio_rtl_tri_io[15]}]
#set_property SLEW SLOW [get_ports {gpio_rtl_tri_io[15]}]
#set_property PULLUP true [get_ports {gpio_rtl_tri_io[15]}]

#set_property -dict { PACKAGE_PIN AB22  IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L10N_T1_D15_14 Sch=ja[1]
#set_property -dict { PACKAGE_PIN AA18  IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]
#set_property -dict { PACKAGE_PIN AB21  IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L10P_T1_D14_14 Sch=ja[2]
#set_property -dict { PACKAGE_PIN AB20  IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
#set_property -dict { PACKAGE_PIN AB18  IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
#set_property -dict { PACKAGE_PIN Y21   IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
#set_property -dict { PACKAGE_PIN AA21  IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L8N_T1_D12_14 Sch=ja[8]
#set_property -dict { PACKAGE_PIN AA20  IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L8P_T1_D11_14 Sch=ja[9]
#set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVDS     } [get_ports { JB_N[1] }]; #IO_L21N_T3_DQS_34 Sch=jb_n[1]
#set_property -dict { PACKAGE_PIN V9    IOSTANDARD LVDS     } [get_ports { JB_P[1] }]; #IO_L21P_T3_DQS_34 Sch=jb_p[1]
#set_property -dict { PACKAGE_PIN W7    IOSTANDARD LVDS     } [get_ports { JB_N[2] }]; #IO_L19N_T3_VREF_34 Sch=jb_n[2]
#set_property -dict { PACKAGE_PIN V7    IOSTANDARD LVDS     } [get_ports { JB_P[2] }]; #IO_L19P_T3_34 Sch=jb_p[2]
#set_property -dict { PACKAGE_PIN Y9    IOSTANDARD LVDS     } [get_ports { JB_N[3] }]; #IO_L24N_T3_34 Sch=jb_n[3]
#set_property -dict { PACKAGE_PIN W9    IOSTANDARD LVDS     } [get_ports { JB_P[3] }]; #IO_L24P_T3_34 Sch=jb_p[3]
#set_property -dict { PACKAGE_PIN Y7    IOSTANDARD LVDS     } [get_ports { JB_N[4] }]; #IO_L23N_T3_34 Sch=jb_n[4]
#set_property -dict { PACKAGE_PIN Y8    IOSTANDARD LVDS     } [get_ports { JB_P[4] }]; #IO_L23P_T3_34 Sch=jb_p[4]
#set_property -dict { PACKAGE_PIN AA6   IOSTANDARD LVDS     } [get_ports { JC_N[1] }]; #IO_L18N_T2_34 Sch=jc_n[1]
#set_property -dict { PACKAGE_PIN Y6    IOSTANDARD LVDS     } [get_ports { JC_P[1] }]; #IO_L18P_T2_34 Sch=jc_p[1]
#set_property -dict { PACKAGE_PIN AB8   IOSTANDARD LVDS     } [get_ports { JC_N[2] }]; #IO_L22N_T3_34 Sch=jc_n[2]
#set_property -dict { PACKAGE_PIN AA8   IOSTANDARD LVDS     } [get_ports { JC_P[2] }]; #IO_L22P_T3_34 Sch=jc_p[2]
#set_property -dict { PACKAGE_PIN T6    IOSTANDARD LVDS     } [get_ports { JC_N[3] }]; #IO_L17N_T2_34 Sch=jc_n[3]
#set_property -dict { PACKAGE_PIN R6    IOSTANDARD LVDS     } [get_ports { JC_P[3] }]; #IO_L17P_T2_34 Sch=jc_p[3]
#set_property -dict { PACKAGE_PIN AB6   IOSTANDARD LVDS     } [get_ports { JC_N[4] }]; #IO_L20N_T3_34 Sch=jc_n[4]
#set_property -dict { PACKAGE_PIN AB7   IOSTANDARD LVDS     } [get_ports { JC_P[4] }]; #IO_L20P_T3_34 Sch=jc_p[4]

#set_property PACKAGE_PIN T14 [get_ports {led_tri_o[0]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led_tri_o[0]}]
#set_property PACKAGE_PIN T15 [get_ports {led_tri_o[1]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led_tri_o[1]}]
#set_property PACKAGE_PIN T16 [get_ports {led_tri_o[2]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led_tri_o[2]}]
#set_property PACKAGE_PIN U16 [get_ports {led_tri_o[3]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led_tri_o[3]}]
#set_property PACKAGE_PIN V15 [get_ports {led_tri_o[4]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led_tri_o[4]}]
#set_property PACKAGE_PIN W16 [get_ports {led_tri_o[5]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led_tri_o[5]}]
#set_property PACKAGE_PIN W15 [get_ports {led_tri_o[6]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led_tri_o[6]}]
#set_property PACKAGE_PIN Y13 [get_ports {led_tri_o[7]}]
#set_property IOSTANDARD LVCMOS25 [get_ports {led_tri_o[7]}]

##set_property PACKAGE_PIN D16 [get_ports {netic20_d16}]; #IO_L5N_T0_16
##set_property PACKAGE_PIN D20 [get_ports {netic20_d20}]; #IO_L19P_T3_16
##set_property PACKAGE_PIN E16 [get_ports {netic20_e16}]; #IO_L5P_T0_16
##set_property PACKAGE_PIN F4 [get_ports {netic20_f4}]; #IO_0_35
##set_property PACKAGE_PIN T3 [get_ports {netic20_t3}]; #IO_0_34
##set_property PACKAGE_PIN Y17 [get_ports {netic20_y17}]; #IO_0_13


#set_property PACKAGE_PIN W21 [get_ports oled_sclk]
#set_property IOSTANDARD LVCMOS33 [get_ports oled_sclk]
#set_property PACKAGE_PIN Y22 [get_ports oled_sdin]
#set_property IOSTANDARD LVCMOS33 [get_ports oled_sdin]
## vbat
#set_property PACKAGE_PIN P20 [get_ports {oled_gpio[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {oled_gpio[0]}]
## vdd
#set_property PACKAGE_PIN V22 [get_ports {oled_gpio[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {oled_gpio[1]}]
## res
#set_property PACKAGE_PIN U21 [get_ports {oled_gpio[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {oled_gpio[2]}]
## dc
#set_property PACKAGE_PIN W22 [get_ports {oled_gpio[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {oled_gpio[3]}]

#set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports { PIC_SS_B }]; #IO_L3N_T0_DQS_34 Sch=pic_ss_b

##DPTI specific signals
#set_property PACKAGE_PIN Y18 [get_ports DPTI_FTCLK]
#set_property IOSTANDARD LVCMOS33 [get_ports DPTI_FTCLK]
#set_property  PACKAGE_PIN U20 [get_ports { DPTI_PDB[0] }]
#set_property  slew "SLOW"  [get_ports { DPTI_PDB[0] }]
#set_property  IOSTANDARD LVCMOS33 [get_ports { DPTI_PDB[0] }]
#set_property PACKAGE_PIN P14 [get_ports { DPTI_PDB[1] }]
#set_property slew "SLOW"  [get_ports { DPTI_PDB[1] }]
#set_property IOSTANDARD LVCMOS33 [get_ports { DPTI_PDB[1] }] 
#set_property PACKAGE_PIN P15 [get_ports { DPTI_PDB[2] }]
#set_property slew "SLOW"  [get_ports { DPTI_PDB[2] }]
#set_property IOSTANDARD LVCMOS33  [get_ports { DPTI_PDB[2] }] 
#set_property PACKAGE_PIN U17 [get_ports { DPTI_PDB[3] }] 
#set_property slew "SLOW"  [get_ports { DPTI_PDB[3] }] 
#set_property IOSTANDARD LVCMOS33  [get_ports { DPTI_PDB[3] }]
#set_property PACKAGE_PIN R17 [get_ports { DPTI_PDB[4] }]
#set_property slew "SLOW"  [get_ports { DPTI_PDB[4] }]
#set_property IOSTANDARD LVCMOS33 [get_ports { DPTI_PDB[4] }]
#set_property PACKAGE_PIN P16 [get_ports { DPTI_PDB[5] }]
#set_property slew "SLOW"  [get_ports { DPTI_PDB[5] }]
#set_property IOSTANDARD LVCMOS33  [get_ports { DPTI_PDB[5] }]
#set_property PACKAGE_PIN R18 [get_ports { DPTI_PDB[6] }]
#set_property slew "SLOW"  [get_ports { DPTI_PDB[6] }]
#set_property IOSTANDARD LVCMOS33  [get_ports { DPTI_PDB[6] }]
#set_property PACKAGE_PIN N14  [get_ports { DPTI_PDB[7] }]
#set_property slew "SLOW"   [get_ports { DPTI_PDB[7] }]
#set_property IOSTANDARD LVCMOS33  [get_ports { DPTI_PDB[7] }]
#set_property PACKAGE_PIN V17 [get_ports { DPTI_OE }]
#set_property slew "SLOW"  [get_ports { DPTI_OE }]
#set_property IOSTANDARD LVCMOS33 [get_ports { DPTI_OE }] 
#set_property PACKAGE_PIN P19 [get_ports { DPTI_RD }]
#set_property slew "SLOW" [get_ports { DPTI_RD }]
#set_property IOSTANDARD LVCMOS33 [get_ports { DPTI_RD }] 
#set_property PACKAGE_PIN N17 [get_ports { DPTI_RXF }]
#set_property slew "SLOW"  [get_ports { DPTI_RXF }]
#set_property IOSTANDARD LVCMOS33 [get_ports { DPTI_RXF }] 
#set_property PACKAGE_PIN P17 [get_ports { DPTI_SIWU }]
#set_property slew "SLOW"  [get_ports { DPTI_SIWU }]
#set_property IOSTANDARD LVCMOS33 [get_ports { DPTI_SIWU }] 
#set_property PACKAGE_PIN R14 [get_ports { DPTI_JTAGEN }]
#set_property slew "SLOW"  [get_ports { DPTI_JTAGEN }]
#set_property IOSTANDARD LVCMOS33  [get_ports { DPTI_JTAGEN }] 
#set_property  PACKAGE_PIN Y19 [get_ports { DPTI_TXE }] 
#set_property slew "SLOW"  [get_ports { DPTI_TXE }] 
#set_property IOSTANDARD LVCMOS33 [get_ports { DPTI_TXE }] 
#set_property  PACKAGE_PIN R19 [get_ports { DPTI_WR }]
#set_property slew "SLOW"  [get_ports { DPTI_WR }]
#set_property IOSTANDARD LVCMOS33 [get_ports { DPTI_WR }]

### USB-HID
#set_property -dict { PACKAGE_PIN W17 PULLUP TRUE IOSTANDARD LVCMOS33 } [get_ports { PS2_Clk }]; #IO_L16N_T2_A15_D31_14 Sch=ps2_clk
#set_property -dict { PACKAGE_PIN N13 PULLUP TRUE IOSTANDARD LVCMOS33 } [get_ports { PS2_Data }]; #IO_L23P_T3_A03_D19_14 Sch=ps2_data

##set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { PRSNT_M2C }]; #IO_L22N_T3_A04_D20_14 Sch=prsnt_m2c
##set_property -dict { PACKAGE_PIN U22   IOSTANDARD LVCMOS33 } [get_ports { PUDC_B }]; #IO_L3P_T0_DQS_PUDC_B_14 Sch=pudc_b
#set_property PACKAGE_PIN T19 [get_ports {qspi_ss_io[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {qspi_ss_io[0]}]
#set_property PACKAGE_PIN P22 [get_ports qspi_io0_io]
#set_property IOSTANDARD LVCMOS33 [get_ports qspi_io0_io]
#set_property PACKAGE_PIN R22 [get_ports qspi_io1_io]
#set_property IOSTANDARD LVCMOS33 [get_ports qspi_io1_io]
#set_property PACKAGE_PIN P21 [get_ports qspi_io2_io]
#set_property IOSTANDARD LVCMOS33 [get_ports qspi_io2_io]
#set_property PACKAGE_PIN R21 [get_ports qspi_io3_io]
#set_property IOSTANDARD LVCMOS33 [get_ports qspi_io3_io]

set_property PACKAGE_PIN W5 [get_ports iic_rtl_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports iic_rtl_scl_io]
set_property PACKAGE_PIN V5 [get_ports iic_rtl_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports iic_rtl_sda_io]

#set_property PACKAGE_PIN W19 [get_ports sd_sck_o]
#set_property IOSTANDARD LVCMOS33 [get_ports sd_sck_o]
#set_property PACKAGE_PIN T18 [get_ports {sd_cd_tri_i[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sd_cd_tri_i[0]}]
#set_property PACKAGE_PIN W20 [get_ports sd_cmd_tri_io]
#set_property IOSTANDARD LVCMOS33 [get_ports sd_cmd_tri_io]
#set_property PACKAGE_PIN V19 [get_ports sd_dat0_i]
#set_property IOSTANDARD LVCMOS33 [get_ports sd_dat0_i]
#set_property PACKAGE_PIN T21 [get_ports sd_dat1_i]
#set_property IOSTANDARD LVCMOS33 [get_ports sd_dat1_i]
#set_property PACKAGE_PIN T20 [get_ports sd_dat2_i]
#set_property IOSTANDARD LVCMOS33 [get_ports sd_dat2_i]
#set_property PACKAGE_PIN U18 [get_ports sd_dat3_i]
#set_property IOSTANDARD LVCMOS33 [get_ports sd_dat3_i]
#set_property PACKAGE_PIN V20 [get_ports {sd_reset_o[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sd_reset_o[0]}]

#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { SD_CCLK }]; #IO_L12P_T1_MRCC_14 Sch=sd_cclk
#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L20N_T3_A07_D23_14 Sch=sd_cd
#set_property -dict { PACKAGE_PIN W20   IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L12N_T1_MRCC_14 Sch=sd_cmd
#set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { SD_D[0] }]; #IO_L14N_T2_SRCC_14 Sch=sd_d[0]
#set_property -dict { PACKAGE_PIN T21   IOSTANDARD LVCMOS33 } [get_ports { SD_D[1] }]; #IO_L4P_T0_D04_14 Sch=sd_d[1]
#set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { SD_D[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sd_d[2]
#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { SD_D[3] }]; #IO_L18N_T2_A11_D27_14 Sch=sd_d[3]
#set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L11N_T1_SRCC_14 Sch=sd_reset


#set_property -dict { PACKAGE_PIN AA13  IOSTANDARD LVCMOS25 } [get_ports { SET_VADJ[0] }]; #IO_L3P_T0_DQS_13 Sch=set_vadj[0]
#set_property -dict { PACKAGE_PIN AB17  IOSTANDARD LVCMOS25 } [get_ports { SET_VADJ[1] }]; #IO_L2N_T0_13 Sch=set_vadj[1]

#set_property PACKAGE_PIN E22 [get_ports {sw[0]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {sw[0]}]
#set_property PACKAGE_PIN F21 [get_ports {sw[1]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {sw[1]}]
#set_property PACKAGE_PIN G21 [get_ports {sw[2]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {sw[2]}]
#set_property PACKAGE_PIN G22 [get_ports {sw[3]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {sw[3]}]
#set_property PACKAGE_PIN H17 [get_ports {sw[4]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {sw[4]}]
#set_property PACKAGE_PIN J16 [get_ports {sw[5]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {sw[5]}]
#set_property PACKAGE_PIN K13 [get_ports {sw[6]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {sw[6]}]
#set_property PACKAGE_PIN M17 [get_ports {sw[7]}]
#set_property IOSTANDARD LVCMOS12 [get_ports {sw[7]}]

set_property PACKAGE_PIN R4 [get_ports SYSCLK]
set_property IOSTANDARD LVCMOS33 [get_ports SYSCLK]

#set_property PACKAGE_PIN AA19 [get_ports UART_RX_OUT]
#set_property IOSTANDARD LVCMOS33 [get_ports UART_RX_OUT]
#set_property PACKAGE_PIN V18 [get_ports UART_TX_IN]
#set_property IOSTANDARD LVCMOS33 [get_ports UART_TX_IN]

#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS25 } [get_ports { VADJ_EN }]; #IO_L13N_T2_MRCC_13 Sch=vadj_en
#set_property -dict { PACKAGE_PIN D15  } [get_ports { VREFA_M2C }]; #IO_L6N_T0_VREF_16 Sch=vrefa_m2c
#set_property -dict { PACKAGE_PIN K14  } [get_ports { VREFA_M2C }]; #IO_L19N_T3_A21_VREF_15 Sch=vrefa_m2c
#set_property -dict { PACKAGE_PIN H18  } [get_ports { VREFA_M2C }]; #IO_L6N_T0_VREF_15 Sch=vrefa_m2c
#set_property -dict { PACKAGE_PIN C20  } [get_ports { VREFA_M2C }]; #IO_L19N_T3_VREF_16 Sch=vrefa_m2c

#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVDS     } [get_ports { XA_N[1] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xa_n[1]
#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVDS     } [get_ports { XA_P[1] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xa_p[1]
#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVDS     } [get_ports { XA_N[2] }]; #IO_L1N_T0_AD0N_15 Sch=xa_n[2]
#set_property -dict { PACKAGE_PIN H13   IOSTANDARD LVDS     } [get_ports { XA_P[2] }]; #IO_L1P_T0_AD0P_15 Sch=xa_p[2]
#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVDS     } [get_ports { XA_N[3] }]; #IO_L2N_T0_AD8N_15 Sch=xa_n[3]
#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVDS     } [get_ports { XA_P[3] }]; #IO_L2P_T0_AD8P_15 Sch=xa_p[3]
#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVDS     } [get_ports { XA_N[4] }]; #IO_L5N_T0_AD9N_15 Sch=xa_n[4]
#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVDS     } [get_ports { XA_P[4] }]; #IO_L5P_T0_AD9P_15 Sch=xa_p[4]

#create_generated_clock -name DDR3_ck_p[0] -source [get_pins {system_i/mig_7series_0/u_system_mig_7series_0_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck/C}] -divide_by 1 -invert [get_ports {DDR3_ck_p[0]}]

#### Displayport v5.0
#set_property PACKAGE_PIN E6 [get_ports DP_LNK_CLK_N]
#create_clock -period 7.407 -name DP_LNK_CLK_P [get_ports DP_LNK_CLK_P]

#set_property PACKAGE_PIN B4 [get_ports {DP_TX_LANE_P[0]}]
#set_property PACKAGE_PIN D5 [get_ports {DP_TX_LANE_P[1]}]

#set_property PACKAGE_PIN AA11 [get_ports DP_AUX_OUT_N]
#set_property IOSTANDARD LVDS_25 [get_ports DP_AUX_OUT_P]
#set_property IOSTANDARD LVDS_25 [get_ports DP_AUX_OUT_N]
#set_property PACKAGE_PIN AB10 [get_ports DP_AUX_IN_N]
#set_property IOSTANDARD LVDS_25 [get_ports DP_AUX_IN_P]
#set_property IOSTANDARD LVDS_25 [get_ports DP_AUX_IN_N]

#set_property PACKAGE_PIN N15 [get_ports DP_HPD]
#set_property IOSTANDARD LVCMOS33 [get_ports DP_HPD]
#set_property PULLDOWN true [get_ports DP_HPD]


